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Design and Implementation of a Multicore Processor Using FPGA

by Ali J. Ibada

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This book presents a study of multicore RISC processor by using FPGA. A 32-bit single cycle MIPS processor is designed using VHDL, which can execute 50 instructions. To reach parallel processing by exploiting Instruction Level Parallelism (ILP), two-way superscalar MIPS processor is designed by duplicating some components of single cycle MIPS processor and added hazard unit. Then, the single cycle MIPS processor subdivided to five pipeline stages 5-stages to obtain pipelined MIPS processor. To increase processor performance memory hierarchy is exploited by adding cache memory to pipeline MIPS processor. A Multicore MIPS processor is achieved by connecting two of complete single core together; these cores operate as separate independent processors within a single chip. Coherency problems are solved by using MESI protocol. All processors are designed using Xilinx ISE 13.4 Design Suite. The entire processor design is configured on a Xilinx Spartan-3AN FPGA starter kit, and the results have been displayed on the 2×16 LCD internal screen of the kit and external VGA screen.

 

 

Details:
rank:
price: $76.00
bound: 212 pages
publisher: LAP LAMBERT Academic Publishing (April 21, 2017)
lang: English
asin:
isbn: 3330073845, 978-3330073845,
weight: 12.8 ounces (
filesize:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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